1. Technical Field
The present invention relates to a Multi-Threshold CMOS (MTCMOS) circuit, and more particularly, to a high speed pulse based flip-flop that has a scan function and a data retention function for use in an MTCMOS circuit.
2. Discussion of the Related Art
Battery dependent mobile devices capable of high performance and low power consumption are becoming increasingly prevalent in the marketplace. To produce these devices, semiconductor circuits having sizes below 100 μm are used. However, when using such circuits, a leakage current may increase during a sleep mode of the mobile device, thus reducing the battery life of the device.
One technique for reducing leakage currents in such small-sized semiconductor circuits is to use a Multi-Threshold CMOS (MTCMOS) circuit. The MTCMOS circuit uses low threshold voltage (low-Vth) CMOS transistors to implement a desired function and high threshold voltage (high-Vth) CMOS transistors to reduce the leakage current during the sleep mode of a semiconductor chip.
For example, when the MTCMOS circuit is powered off, in the sleep mode, the contents stored in a flip-flop of the MTCMOS circuit are deleted. Thus, the previous state of the MTCMOS circuit cannot be restored upon returning to a normal mode. To restore data of a previous state of the MTCMOS circuit, a retention flip-flop has been used. However, here, a high threshold voltage transistor must be used to retain the data and reduce the leakage current, thereby reducing the performance of the retention flip-flop.
One technique for reducing a delay in data input to output time due to a scan function and a retention function is to use a pulse based flip-flop and a separate latch for performing a data retention function and a flip-flop for performing a scan function. In this configuration, the scan function and the retention function are selectively performed to prevent an operating speed of a semiconductor chip from decreasing.
FIG. 1 is a circuit diagram of a conventional master slave flip-flop 10 having a data retention function. Referring to FIG. 1, the conventional master slave flip-flop 10 includes a separate retention latch unit 11 for retaining data when the flip-flop 10 is powered off. Even when the flip-flop 10 is powered off, power is supplied to the retention latch unit 11.
The conventional master slave flip-flop 10 also includes master terminal 13 and a slave terminal 15. The flip-flop 10 stores a value of the slave terminal 15 in the retention latch unit 11 before the flip-flop 10 is powered off. Therefore, even though data stored in the master and slave latches 13 and 15 is deleted, data stored in the retention latch unit 11 can be retained since power continues to be supplied to the retention latch unit 11. When the flip-flop 10 is powered on, data stored in the retention latch unit 11 is transferred to the slave terminal 15 to restore the conventional master slave flip-flop 10 to an original state.
FIG. 2 is a circuit diagram of a conventional master slave flip-flop 20 having a scan function. Referring to FIG. 2, the conventional master slave flip-flop 20 determines whether to capture a data value D in a normal mode or a test value TI in a test mode according to a test enable signal TE. When the test enable signal TE is logic 1, the test mode is activated to perform a test operation. When the test enable signal TE is logic 0, the normal mode is entered and a normal function is performed.
Although the combination of the conventional master slave flip-flop 10 and the conventional master slave flip-flop 20 enables the scan function and the data retention function to be selectively performed; however, when the scan function is applied to the conventional master slave flip-flop 10, a data input to output time is delayed, thereby reducing the operating speed of the semiconductor chip. Accordingly, there exists a need for flip-flop that is capable of performing a scan function and a data retention function without increasing the data input to output time.